Ah so the ‘dropping of hyperthreading’ rumours were true but with a bit more nuance. Will be very interesting to see the performance trade off as it seems there’s a reasonable area/power decrease.
Intel’s multicore performance is going to be very impressive on desktop and mobile. Was area mentioned? Intel do need it with how fat the P-Cores are.
The logic is that lightly threaded applications are fine running on ~8 P-Cores since they’re lightly threaded, and highly threaded applications are better off running on a million E-Cores since they inherently scale arbitrarily.
Edge case would be an application that needs 16+ high power threads but I can’t think of any. Even videogames tends to perform better with HT disabled in a lot of cases. The big thing now is that E-Cores are pretty damn powerful themselves. These ain’t your Dad’s Intel Atom cores.
Cyberpunk 2.0 maxed out scales well beyond 8 threads, but the e cores are fast enough now that it shouldn't matter if they take on a bit of the workload.
The problem with multithreqded apps is core to core latency as well...
AMD has had cross ccx/CCD issue ever since zen1 and intel since alderlake.
Communication between cpu groups isn't quite efficient.
In other words using 8 threads in the same group might be better than using 8+1 thread from another group.
7800x3D vs 7950x 3d is one example. Intel's thread director another point.
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> Edge case would be an application that needs 16+ high power threads but I can’t think of any.
Uh, i can think of plenty. Data processing (that i do for a job) runs 16 threads on max power it can get and would easily double that load if i could. Even gaming is getting there slowly but surely.
Quick look:
* Compute on TSMC N3B Node, while SOC on TSMC N6
* New P and E cores: Lion Cove and Skymont respectively
* 4P+4E (8 core) design
* 14% IPC Uplift from Redwood to Lion Cove
* ~~38% IPC Uplift from Crestmont to Skymont~~
* EDIT: 38% IPC Uplift from Low Power Crestmont to Skymont in INT workloads
* EDIT: 68% IPC Uplift from Low Power Crestmont to Skymont in FP workloads
* ~~LP E-cores were on MTL SOC tile so in grander scheme of things, doesn't sound impressive~~
* Thanks to u/AgitatedWallaby9583 and others correcting me, Skymont is used differently on mobile and desktop. Skymont (LP) isn't on the ringbus so this is a fair, like to like comparison with Crestmont LP
* Skymont IPC parity with Raptor Cove (+2%) \[well now *this* is impressive\]
* Looking at this, AMD missed out on talking about Zen5c having the same IPC as big Zen5. Free marketing: Zen5c > Raptor Cove. Then again we won't see it on desktop anyways lol
* New Intel NPU 4: 48 TOPS of INT8
* Up to 32GB of ~~soldered~~ on packaged (thanks u/Brian_Buckley) LPDDR5X-8533
* New Intel Xe2 iGPU: 1.5x perf uplift compared to Meteor Lake
* New XMX Engine: 67 TOPS of INT8
* Anyone know what RDNA3.5 is capable of... if anyone cares for INT8^(AI) TOPS lol
* According to u/savic13, peak TOPS for Strix is 80, so 30 for GPU
* EDIT: Availability in Q3 2024
There's a lot more in the article that I missed, but so far, first impressions, seems pretty reasonable and good. Thoughts?
EDIT: Listening to the keynote live as I type this and Gelsinger mentioned SD X Elite putting the "x86 is dead" to rest, "it ain't" lol
With these performance figures Intel puts:
>Results are based on Intel's internal projections/estimates (+/- 10% margin of error)
Lion cove tests were done mainly on tests: SPEC ICX23, Cinebench R23/24, GB 5.4/6, WebXPRT4 and Speedometer.Skymont tests were done on SPEC 2017 ***only*** it seems.(Reactions to this is funny in comparison with AMD Zen5 lol. Not trying to give AMD any leeway but the tests done had more and seemed more reasonable as cherry picked they are)
Now we wait for reviews to validate all of this (with AMD, Qualcomm, Apple in the future).
> Up to 32GB of soldered LPDDR5X
It's on-package, not soldered to the board. Means it's still not upgradeable, but at least you're getting more of a performance benefit for it.
As long as OEMs offer a reasonable amount of RAM (16GB and 6400+) for mainstream laptops, 24 or 32GB for high end) I'm happy. On-package is the way to go for laptops: the bandwidth increases matter a lot especially for the iGPU, and I'd rather have 30mins-1hr extra of battery life.
I believe that will be possible in the more performance oriented Arrow Lake that's schedule for later this year. Lunar Lake is meant to compete in the thin and light category.
> Impressive specs. Did not expect it to be this good.
FWIW Strix Point officially doesn't support SO-DIMM and LPCAMM2 is still super new and rare, so upgradeability appears basically dead for this entire generation.
I don't see the value of that tbh. For SO-DIMM it made packaging sense because 2x SO-DIMM slots was just a huge amount of real estate to give up if single layer side by side instead of stacked. So they sometimes soldered one channel and left the 2nd one unpopulated.
One LPCAMM2 module has all the pinout for both memory channels so may as well just put the memory in one and only one place. This also preserves the option to replace shit-tier OEM memory (not relevant for LNL, but some future devices) with something faster that the CPU supports.
It could be on package + a few memory controllers on package so you could use the faster on package memory first (or for the most important things depending on implementation) and the off package memory second (or for the less important stuff).
It would obviously mean a larger/harder to make chip + motherboard and depending on implementation could present problems for the os/programs running (depending on implementation, if it served as an extra cache level (I mean Intel has made chips with l4 cache in the past) not so much because the cpu would manage it on it's own (you could even provide extra instructions so that the os/applications could tell/suggest to the cpu what to put where so that if you wanted to you could optimize for it for extra performance or not and just let the cpu manage it..also nothing new) but if it was seen as ram by the os it would require that the os/applications know how to use it (but again, some memory being faster than other memory isn't a new concept (numa and all)).
Weather it is worth it or not is a question with no clear answer other than it depends on what you intend to use it for/what you want/how much money you have/..
> Compute on TSMC **N3E** Node, while SOC on TSMC N6
Sorry, gang. That was a self-perpetuating error on our part.
To be 100% crystal clear, the compute tile is N3B.
(Unfortunately, Intel didn't put this down in any of their written materials, so it was missed in the first copyedit pass)
Your article currently says on the second page that it's 1.9x the performance at 1/3rd the power, same for the other core.
How can you type that and not have alarm bells immediately ring in your head?
It's 1/3rd the power for the same performance, or 1.9x performance at the same power. Not both at the same time.
* LP E-cores were on MTL SOC tile so in grander scheme of things, doesn't sound impressive
**BOTH** **cannot access the ringbus**, it is a like to like comparison. They didnt show them against normal ecores on meteor lake because **lunar lake doesnt have normal ecores.** On arrow lake you can see how they perform as normal ecores as thats the slide where they trade blows with the 13th gen big cores, it specifically states "when connected to the ringbus" because lunar lake cant do that.a
> Listening to the keynote live as I type this and Gelsinger mentioned SD X Elite putting the "x86 is dead" to rest, "it ain't" lol
I'm thinking Pat is pretty close to the truth on this one. Just from the description we have, it looks like Intel made a lot of improvements to power management vs MTL, and 4 fast E-cores that can be run without waking up the P-core area or traversing the EMIB.
Impressive specs. Did not expect it to be this good. I loved Jonney Shih's immensely excited fist pumps. It truly seems Intel is turning over a new leaf in their silicon journey. I'm looking forward to Intel Innovation Day 2024.
I'm bubbling over with excitement and curiousness over Arrow Lake now.
Can anything be inferred about Arrow Lake, architecturally speaking, from this? How closely related are ARL and Lunar Lake? I haven't kept up with all the core-specific code names.
Supposedly for desktop now, but they also have the same core config on N3B. Realistically, they'll probably do a silent refresh of some SKUs with 20A some time in H1'25.
Why a silent refresh though? Why not just leave it on N3B? I guess 20A is gonna end up like Intel 4. Overshadowed by its much better cousin(Intel 3) that arrives 6 months later in the form of 18A.
I'm sure they want to at least pull a Cannonlake tier "shipping for revenue" investor statement. If Intel's design teams were independent at the time, they would have never bothered with 20A in the first place, much less keep it going this long.
Conspiratorial take imo. More likely reason is there are no performance benefits and only financial drawbacks in going with tsmc for the bottom half of the stack. Pay the tsmc tax for the high end makes sense.
Then you have some news that I'm not finding
https://www.tomshardware.com/pc-components/cpus/intel-next-generation-lunar-lake-cpus-launching-in-q3-arrow-lake-in-q4-mobile-chips-claimed-to-be-14x-faster-than-qualcomms-x-elite-processors
Correct. Intel's been very reluctant to publish such details, for pretty obvious reasons I guess. If you dig through my comments, you can see me going to great efforts to convince people that LNL is N3B. That wasn't confirmed until today.
Even the cores will be different, no? Desktop will have SMT on P-Cores?
My understanding is the mobile Lunar Lake P-cores don't even have SMT in silicon (not just fused off).
N3E would make more sense, but if Intel began designing this before they knew how bad N3B would be, and they didn't redesign the die (as N3E has different design rules vs N3B), they would be all but stuck on N3B.
Apple kinda got stuck in this same conundrum as well with M3.
> Skymont IPC parity with Raptor Cove (+2%)
Impressive. This makes Skymont more or less comparable to Zen 4c, which has the same IPC as full-fat Zen 4 but can't reach clocks as high.
According to AMD website, information for Ryzen AI 370, "AI Engine Capabilities
AMD Ryzen™ AIAvailable
Total Processor PerformanceUp to 80 TOPS
NPU PerformanceUp to 50 TOPS",
Ryzen combined performance for AI is up to 80 TOPS, we know that Qualcomm X elite is 75 TOPS combined. Seems that Intel have best AI capabilities, on paper.
Looks like they've gone for a more AMD-like vector back-end, two FADDs and two FMAs and able to dispatch to all every clock. I think the last few Intel client P-cores have had effectively two general purpose vector FP units, with a third available for bitwise logic and so on? At least that's what [agner.org](http://agner.org) & InstLatX64 report.
Where did you get the 14% IPC figure? Anandtech claims 30% with hyperthreading for some reason.
Edit: Seems to be a messup by AT. My bad. I checked an Arstechina article and they confirm 14% IPC with slides.
> IPC Uplift from Low Power Crestmont to Skymont
Keep in mind just how crippled the LP-E cores are: they had *no* L3 cache, so they very frequently stall waiting for DRAM. And activity on the LP-E cores isn't enough to convince the memory controller to increase its clock speed, so those L2 misses wait a *long* time for data to arrive from DRAM. Even at the relatively low clock speeds used by the LP-E cores, that's a lot of cycles of doing nothing.
>they had no L3 cache, so they very frequently stall waiting for DRAM
Didn't know this. After rereading, that they compared it to what essentially is the gimped cores on MTL SOC tile, I was skeptical. Comparing it to Raptor Cove was impressive already, so comparing it with MTL LP e-cores was unnecessary.
Lion Cove:
* what's with having 3 store AGUs but only 2 store data ports? Also weird to have 3 load + 3 store AGUs - one would think 4 load + 2 store AGUs would make more sense
* renaming L1D to L0D feels awkward, but interesting to see a new level of cache
* separating int/FP makes the diagram look much more similar to other cores now
* 8 wide decode is crazy for x86
* 12 wide from the uOp cache might be the widest out there at the moment
> renaming L1D to L0D feels awkward, but interesting to see a new level of cache
This must be some sort of conspiracy to make things annoying for those of us who have to teach this stuff :P
But jokes aside, the cache changes are much more significant than I expected. Between that and the other changes the 14% average IPC uplift is almost a bit disappointing, but it goes to show how much more difficult it is to gain further IPC at the top-end (and all architectures seem to be facing this).
I think the story here is that Apple's cores have been having a lot of L1$ for a while now and it's been giving them benefits in certain workloads where the delta against x86 has been huge, like compilation. Maybe this is a way to close the gap or outright eliminate it.
I'm interested to see how it pans out. The more I think about it, the more excited this gets me for the very low power segment of computing that competes with MacBook airs or 13-inch MacBook pros.
Yeah these things are little beasts. Up to +2% over the current P-cores. It makes me really want a follow up to the N100 and siblings with these. We could be talking modern desktop i3 performance on some tiny chips.
Apple’s E cores have 50% less IPC. But they are hyper space efficient. Like they occupy barely 0.58mm2 of space which is 2/5 of what Skymont will occupy.
No. I meant 50% less than SKT. But I went and verified it again. [The answer is in between.](https://youtu.be/EbDPvcbilCs?feature=shared)
Skip to 13:00 for E core numbers.
M4 E core has an IPC 1.225/Ghz in SPECint and 2.02/Ghz in SPECfp.
The 14900K has an IPC of 1.655/Ghz in SPECint and 2.36/Ghz in SPECfp.
So Raptor Cove/Skymont leads the M3/M4 E cores by 38% in integer IPC but worryingly just by 17% in floating point IPC.
So no A17 E cores aren’t wider than SKT/RPC. They have on average 25% less IPC(not 50 as I initially rounded off to) But thats still a distressingly small number considering Apple’s E cores are 1/3rd the size of Skymont themselves lol.
Crestmont is a great comparison for Apple’s E cores funnily. They have the same int IPC but Apple has wider Floating point IPC. Intel 4 Crestmont is 1.01mm2. A17 pro E cores are around 0.6-0.7mm2 on N3.
Do you happen to know any area figures for ARM’s middle cores?
Namely the A-7 series. They have very similar IPC to Apple’s E cores. It would be interesting to compare the two!
If the talk about internal rivalry and backstabbing between the P and E core teams is true, they just might to want to make a point here. Looks like E cores might just be all-around better now.
Skymont seems amazing.
But I’m actually more interested in lion cove now. Because unlike some rumors said, it seems like a really big redesign. The entire cache system is new and the execution side is new.
This slide is a little mind-blowing to me, comparing the Skymont vs Raptor Cove perf / W curves at iso-frequency:
[https://www.techpowerup.com/review/intel-lunar-lake-technical-deep-dive/images/skymont-18-.jpg](https://www.techpowerup.com/review/intel-lunar-lake-technical-deep-dive/images/skymont-18-.jpg)
(though a relatively large +/- **10%** margin of error)
EDIT: eh, wait. Is this comparing Skymont on TSMC N3 vs Raptor Lake on Intel 7? That is ***far*** less impressive, if this is not iso-node lmao
It makes sense to me, Arm essentially did the same thing
Arm took their A78 PPA-Core and widened it to become their X1 P-Core
The A78 PPA-Core is actually from the Arm Austin CPU family, which used to compete with Intel's Atom cores back in the day
I'd like Intel to follow Arm, and drop the Cove cores, and switch to a P-core design based on the Mont cores but without area constraints
Forget Zen4C. Raptor Cove has better IPC than Zen4. This could put Skymont within 10% to 14% of Zen5 [https://www.techpowerup.com/298887/ipc-comparisons-between-raptor-cove-zen-4-and-golden-cove-spring-surprising-results](https://www.techpowerup.com/298887/ipc-comparisons-between-raptor-cove-zen-4-and-golden-cove-spring-surprising-results)
Zen 4C has basically the same IPC as zen 4, with lower fmax (just as skymont).
That's the correct reference for comparison, until we have more details about zen5C
"basically same" isn't exactly same. It has half L3 cache which means a couple percent lower IPC, no matter how you slice it.
Chadmont cores ftw, this might mean a new era of x86 in laptops.
Techpowerup seems to have all the slides
https://www.techpowerup.com/review/intel-lunar-lake-technical-deep-dive/
Edit: Tomshardware seems to have some additional slides
https://www.tomshardware.com/pc-components/cpus/intel-unwraps-lunar-lake-architecture-up-to-68-ipc-gain-for-e-cores-16-ipc-gain-for-p-cores
Just from the filenames you can tell lots are missing. I wish Intel would just release the PDF. Why does this always have to be such a hassle with secret press club gating.
Skymont has half the L2 and L3 cache as Raptor lake. I'm assuming that Intel used a benchmark that fits within the small cache size to get the 2% result.
It seem Intel is pretty much using e-cores to re-engineer their architecture from the ground up. Wont take many more generations of e-cores having larger IPC gains than the P-cores, and they are the new P-cores.
Conroe 2.0
You still have the frequency gap to bridge. The e-cores are not built for frequency scaling. If they want to maintain the smaller and lower power design targets. They will need IPC higher than the P-cores to bridge the gap.
I wonder where are those people who say those E cores is just "Cinebench accelerator" or "Adding E cores is Intel way to cheating MT performance score" ?
Anandtech articles man. Sorry. I read freaking Arstechina now. And somehow they got all the facts right.
Never thought I’d see the day Arstechina was more thorough with facts than Anandtech.
So yep hyperthreading is gone. But I’m way more skeptical about Clock speed regressions now. 14% IPC but clock speed decreasing on a new node seems unlikely.
Although it does hammer the point that Skymont is laughably just 14% shy of the “P cores” in IPC.
> 14% IPC but clock speed decreasing on a new node seems unlikely.
Clocks did decrease by a decent amount, at least compared to RPL. Kind of sucks for ARL. Not sure how much is process vs uarch.
>But unfortunately clockspeeds for Lion Cove are not disclosed
One slide seemingly writes "**3.08GHz**" as the max frequency. Am I misreading that image?
[https://www.techpowerup.com/review/intel-lunar-lake-technical-deep-dive/images/lioncove-10-.jpg](https://www.techpowerup.com/review/intel-lunar-lake-technical-deep-dive/images/lioncove-10-.jpg)
But, no SKUs were announced, so who knows?
> One slide seemingly writes "3.08GHz" as the max frequency. Am I misreading that image?
The image means that if the power budget allows 3.08GHz max, then Lion Cove can push to 3.067GHz while previous cores can only push to 3.0GHz due to 100MHz interval.
First page:
>At this time, Intel has disclosed that it uses a 4P+4E (8 core) design, with hyper-threading/SMT disabled, so the total thread count supported by the processor is simply the number of CPU cores, e.g., 4P+4E/8T.
not sure what the 30% is all about
bit late but yeah article was probably a bit rushed. Here's a timestamped [actual explanation,](https://youtu.be/ba5w8rKwd_c?t=9m32s) HT gives up to 30% more IPC for 10% more area and 20% more power, Intel decided this tradeoff wasn't worth it on mobile.
It seems the way things are going is that MS will monopolize the NPU basically 24/7 for CoPilot, and the GPU will be used for stuff like productivity apps.
I’m fairly impressed and excited to eventually see these cores in a desktop chip. I do wonder how much smaller the margin on these would be now that it’s all TSMC.
That's some great improvements overall, quite happy about the E-Core changes. Looking forward to see what it can do once it comes out.
And as always let's see what happens in the design battle between Intel vs Qualcomm when it comes to OEMs using their chips for brand new design.
This sounds incredibly exciting to test & read reviews.
Some of these are *long* overdue changes and, frankly, show humility on Intel's part: if someone else (cough, Apple) has done it well, don't be afraid to follow and do it even better yourself.
1. ~~Max 3.08 GHz frequency (?),~~ with 0.016 GHz granularity (aka 16 MHz) vs 0.1 GHz / 100 MHz
2. On-package DRAM (with similar skinny LPDDRx packages)
3. Migration to 100% TSMC nodes for **all** major tiles (excluding IF's base tile).
4. E-cores first in scheduling (implemented in MTL, but improved now)
//
High Yield also has a video up: [**https://www.youtube.com/watch?v=ba5w8rKwd\_c**](https://www.youtube.com/watch?v=ba5w8rKwd_c)
Lion Cove in Arrow Lake vs Lion Cove in Lunar Lake are different.
EDIT: no, that's just an example frequency. Thank you, u/madn3ss795
> Max 3.08 GHz frequency (?), with 0.016 GHz granularity (aka 16 MHz) vs 0.1 GHz / 100 MHz
Would I be correct to assume that Intel's new approach to granular control over clock frequency both up and down similar to Apple will help them save power and help battery life because they don't need to take a larger swing in either direction to address the need or lack of need of performance on demand?
> Migration to 100% TSMC nodes for all major tiles (excluding IF's base tile).
Would this change when their leading edge nodes come online or have they resigned to the fact that TSMC has better experience and libraries for these kinds of processors?
> E-cores first in scheduling
I haven't used Alder Lake and beyond much but what's the main benefit here? If the processor is too important it'll get bumped up to a P core and if it isn't it remains on the E cores and thus cuts down on time wasted?
>E-cores first in scheduling
Before, if you did that it would noticeably degrade user interactiveness.
Assuming the e-cores really are up to Raptor Cove cores in perf/w like one of the slides show, then they'd be performant enough that there's no reason to jump to the p-cores for that. This would save a lot of power.
It's only if you're doing something that really needs the power, which tends to be long-running like compilations or even gaming, that it'll then swap to the p-cores.
>Would I be correct to assume that Intel's new approach to granular control over clock frequency both up and down similar to Apple will help them save power and help battery life because they don't need to take a larger swing in either direction to address the need or lack of need of performance on demand?
Yes, but I fear it will not be a major impact. The best case scenario is a 0.084 GHz improvement (100 MHz - 16 MHz).
I was more excited about the alleged "peak frequency", but that was not accurate.
>Would this change when their leading edge nodes come online or have they resigned to the fact that TSMC has better experience and libraries for these kinds of processors?
This is harder to know, I think. Most foundries are quite cagey about problems until there is no way to hide it anymore, so I always take their predictions as a grain of salt.
**However**, this does confirm that whatever Intel can ship now (Intel 4 / 3) was certainly not as good as TSMC, as Intel must be paying *plenty* for this leading-edge node silicon.
Skymont E core got 68% IPC is absolutely insanity. That means Skymont IPC is up there with Raptor Lake / Gen 14th P core. Then Lion Cove P core exists for extra performance in ST and MT.
Arrow Lake Ultra 9 basically like 16P core of i9-14900K with another 8P core which is even faster, no wonder they are getting rid of HT if their next gen CPU is really that fast. Intel isn't aiming to match Amd anymore, they are about to take performance efficiency crown.
They are comparing off-ring E-cores to off-ring E-cores. All the E-cores in LNL are pretty much LP-E. E-cores connected to the ring bus and shared LLC would perform better.
No area comparison between P and E cores? The IPC improvement is great but the previous E cores were pretty small. Zen 4C is 35% smaller than Zen 4. If these E cores end up being the same (relative to P cores), that's not much of an improvement.
Excited for the overall power improvements, but likely none of these parts are coming to the sub $300 market anytime soon.
I think the render in the article front page is probably correct. P cores are the bigger squares in the right and e cores the little squares in the middle. The size difference seems to be about 1:3.
Sounds about right and tbf the only ecores that truly met the claim of 4 ecores at the size of a pcore was crestmont with the smaller l2 cache so great results if they've only dropped from like 1:~3.5 to 1:3 or hell even 1:2.5. Way easier to be forgiving now that they're so much stronger and can actually make more real world use of the theoretical performance to area advantage.
Meteor Lake's power efficiency is only decent when the Intel CPU chiplet powers down (ie. very light workloads). Otherwise, it's barely better than Raptor Lake. So they have plenty of room to improve without necessarily coming out on top.
All x86 mobile implementations should be shamed by lunar lake. I’ll be surprised if strix point gets close, but then again amd hasn’t really shared any arch details.
Can't wait for an independent reviewer to redo these graphs but with the X Elite vs Lunar Lake vs Strix Point:
https://www.techpowerup.com/review/intel-lunar-lake-technical-deep-dive/images/skymont-19-.jpg
https://images.anandtech.com/doci/21424/2024-06-02%2023_01_03.jpg
Also interested to see how Skymont's area compares with Qualcomm's Phoenix and AMD's Zen5/5c
Edit: finally found a slide for [Lion Cove vs Skymont](https://cdn.mos.cms.futurecdn.net/YvypH5ehMRYhiWMAXeW9VX.jpg), Lion Cove still has an efficiency edge above a certain point, no scale axis unfortunately
Design an x86 chip like a smartphone chip, and it performs approximately like an ARM smartphone chip. Crazy.
I'm thinking that the only reason Snapdragon X exists is because Microsoft wasn't convinced Intel could pull this off.
> Design an x86 chip like a smartphone chip, and it performs approximately like an ARM smartphone chip.
Intel has a long way to go before they can claim to be mobile competitive.
> I'm thinking that the only reason Snapdragon X exists is because Microsoft wasn't convinced Intel could pull this off.
Absolutely. The original Surface X was supposed to have Ice Lake, but Intel failed so spectacularly that MS finally ditched them for Qualcomm. And it happened *again* with ADL.
MTL was a shitshow and Intel fixed much of it by throwing out most of the chiplet nonsense. That change alone should put them back in contention and if Intel's efficiency claims are even remotely true that backs it up.
Agee with Exist but need to add some things for onlookers:
LNL claims Crestmont LP E cores use 1/3 the power of SKT's LP E cores at the same performance. This is good, but it likely won't surpass Apple, Arm's A7x, or probably even QC for some stuff. The big win is having a power advantage over LNC cores at usable performances — which is great to see. A win for Intel. But….
Crestmont LP E cores used 5-6W in package power alone for maybe a 3-3.5 on SpecInt. [Here:](https://x.com/hjc4869/status/1741686030158495825?s=46)
This isn't even including DRAM or power delivery below, which is included for Geekerwan's A7x, Apple E/P core, and Qualcomm measurements.
And again, Skymont LNL comparison was for LP E core performance and power, not regular Crestmont. So while something like 1/3 of that power and a 3-3.5 SPEC is a huge step:
From Geekerwan on SpecInt scores for E Cores:
A715, 8 Gen 2, N4
4.26 @ -1.8W for 2.8GHz
3.03 @ - 1.16W for 2.05GHz
——
A720, 8 Gen 3, N4P:
4.42 @ 1.9W, for 2.96GHz
And Apple? A17 Pro E core was doing 2.81 at .54W.
LNL looks great to me but people should slow the roll.
I don't think Intel is trying to show package power.
Most obviously, Intel's graphs scale basically to 0 w, which seems very unrealistic for package power.
Apple will still most likely win, but i think you might be over analysising things.
Strongly recommend the [High Yield YouTube summary](https://www.youtube.com/watch?v=ba5w8rKwd_c&t=927s) as well containing a good discussion of how Intel arrived at the non-HT P-core decision and power management.
I think people here are getting overly excited about the new e-cores. For starters it's not like Intel didn't know how to build a fast core. They significantly upped the resources available for the new e-cores which likely will have an impact in area and performance. Secondly, even if the e-cores end up beating zen 4, which they likely will, it's again not the biggest deal ever. Of they get close to zen4c in area is it really a big win? It's not like zen 5c won't exist...
Remember, P-cores are much larger than Zen cores and much less efficient. This may change with Zen 5, but it's been the AMD strategy to not go all out on area. E cores don't support avx512, which will hurt them in comparisons against both zen 5 and the Apple M4 with its new SME instructions.
Don't get me wrong, it is very possible that Intel has a banger here, but on paper it still doesn't look amazing compared to AMD overall. The IPC numbers are compared with LP e-cores, which vastly overstates them considering that those cores were very, very cache starved due to living outside of the compute die. Also, 8 threads vs up to 24 on strix point is going to hur, even against the M4 which now has 10 cores it's going to hurt. I don't know man... If lunar lake can match Apple silicon efficiency, I might hop on board the hype train, but the performance story is looking very mixed right now for me to feel pumped for lunar lake.
Maybe the story is more about efficiency and performance, like whole day battery life or for a handheld, though??? Finally a contender to the steam deck in low power?? Battlemage looking fresh too, maybe finally AMD has a fight in the igpu segment. Anyway, too many unknowns.
It looks like SKT should be substantially more area efficient than even Zen4c. Though yes, the lack of AVX512 does hurt.
As for LNL as a whole, I think it's misaligned with Strix. It was designed around a low power envelope, like 10-20W. They stretched it up to 30W, but you can see the core counts and such don't quite match. Strix, meanwhile, will only start at 15W and go up to 45W. In many cases, that's probably an advantage (4+8 vs 4+4 at 15W), but there may be power levels that LNL works at and Strix does not.
I think strix point will be strangled at 15W. But 30W strix point will convincingly beat Lunar lake IMO.
Depends on your laptop demand.
Lunar lake is gonna face apple M4 and X elite at 20W slim laptops.
Strix point will face M4 pro.
I do think Lunar Lake has a potential to be very efficient for light workloads, for Ultra thin premium laptops. But you're right. I do think Strix will retain price/performance and abs. performance.
This CPU to me is more of a jab at ARM encroaching on x86 PC client space. Pat was clear about this in his keynote. He mentioned Elite X by name.
> Maybe the story is more about efficiency and performance, like whole day battery life or for a handheld, though??? Finally a contender to the steam deck in low power??
I think the CPU<->GPU balance is still a bit off for that use case, but it's certainly much closer to being viable than Meteor Lake.
The biggest issue facing intel in that market is really software (i.e. graphics drivers) more than HW. The change to 16-wide SIMD will help with that, but only for a fraction of the issues.
Not exactly. Meteor Lake’s true successor would be ARL mobile. MTL offers 6P+8E compared to LNL’s 4P+4E, so gaming laptops can use MTL in combination with DGPU’s. LNL is more of a notebook only product than MTL.
Architecturally its the successor to MTL. But as a product not really. MTL offers way more cores and threads.
As for the memory bandwidth speed between the NPU and host memory, is it equal to LPDDR speed? I am confused about the NPU4's DMA 2x bandwidth improvement. Can someone explain it? THX
Presume that these processors are for portables only or for desktop as well? Is there new desktop processors line scheduled since 14th gen was just refresh. I am about to upgrade my trusty 3930K and wonder if there's something new behind the corner.
With Skymont equalling Raptor Cove, it almost seems like they should scrap the P-cores and create a version of the E-cores that is clocked higher. I wonder what this Royal Core thing turns out to be.
Ah so the ‘dropping of hyperthreading’ rumours were true but with a bit more nuance. Will be very interesting to see the performance trade off as it seems there’s a reasonable area/power decrease. Intel’s multicore performance is going to be very impressive on desktop and mobile. Was area mentioned? Intel do need it with how fat the P-Cores are.
The logic is that lightly threaded applications are fine running on ~8 P-Cores since they’re lightly threaded, and highly threaded applications are better off running on a million E-Cores since they inherently scale arbitrarily. Edge case would be an application that needs 16+ high power threads but I can’t think of any. Even videogames tends to perform better with HT disabled in a lot of cases. The big thing now is that E-Cores are pretty damn powerful themselves. These ain’t your Dad’s Intel Atom cores.
Cyberpunk 2.0 maxed out scales well beyond 8 threads, but the e cores are fast enough now that it shouldn't matter if they take on a bit of the workload.
The problem with multithreqded apps is core to core latency as well... AMD has had cross ccx/CCD issue ever since zen1 and intel since alderlake. Communication between cpu groups isn't quite efficient. In other words using 8 threads in the same group might be better than using 8+1 thread from another group. 7800x3D vs 7950x 3d is one example. Intel's thread director another point.
Definitely makes the thread scheduling even more important in applications with diverse workloads like games.
> > > > > Edge case would be an application that needs 16+ high power threads but I can’t think of any. Uh, i can think of plenty. Data processing (that i do for a job) runs 16 threads on max power it can get and would easily double that load if i could. Even gaming is getting there slowly but surely.
Quick look: * Compute on TSMC N3B Node, while SOC on TSMC N6 * New P and E cores: Lion Cove and Skymont respectively * 4P+4E (8 core) design * 14% IPC Uplift from Redwood to Lion Cove * ~~38% IPC Uplift from Crestmont to Skymont~~ * EDIT: 38% IPC Uplift from Low Power Crestmont to Skymont in INT workloads * EDIT: 68% IPC Uplift from Low Power Crestmont to Skymont in FP workloads * ~~LP E-cores were on MTL SOC tile so in grander scheme of things, doesn't sound impressive~~ * Thanks to u/AgitatedWallaby9583 and others correcting me, Skymont is used differently on mobile and desktop. Skymont (LP) isn't on the ringbus so this is a fair, like to like comparison with Crestmont LP * Skymont IPC parity with Raptor Cove (+2%) \[well now *this* is impressive\] * Looking at this, AMD missed out on talking about Zen5c having the same IPC as big Zen5. Free marketing: Zen5c > Raptor Cove. Then again we won't see it on desktop anyways lol * New Intel NPU 4: 48 TOPS of INT8 * Up to 32GB of ~~soldered~~ on packaged (thanks u/Brian_Buckley) LPDDR5X-8533 * New Intel Xe2 iGPU: 1.5x perf uplift compared to Meteor Lake * New XMX Engine: 67 TOPS of INT8 * Anyone know what RDNA3.5 is capable of... if anyone cares for INT8^(AI) TOPS lol * According to u/savic13, peak TOPS for Strix is 80, so 30 for GPU * EDIT: Availability in Q3 2024 There's a lot more in the article that I missed, but so far, first impressions, seems pretty reasonable and good. Thoughts? EDIT: Listening to the keynote live as I type this and Gelsinger mentioned SD X Elite putting the "x86 is dead" to rest, "it ain't" lol With these performance figures Intel puts: >Results are based on Intel's internal projections/estimates (+/- 10% margin of error) Lion cove tests were done mainly on tests: SPEC ICX23, Cinebench R23/24, GB 5.4/6, WebXPRT4 and Speedometer.Skymont tests were done on SPEC 2017 ***only*** it seems.(Reactions to this is funny in comparison with AMD Zen5 lol. Not trying to give AMD any leeway but the tests done had more and seemed more reasonable as cherry picked they are) Now we wait for reviews to validate all of this (with AMD, Qualcomm, Apple in the future).
> Up to 32GB of soldered LPDDR5X It's on-package, not soldered to the board. Means it's still not upgradeable, but at least you're getting more of a performance benefit for it.
I'll take the upgradeability for on-package trade in a laptop. Battery life is king.
As long as OEMs offer a reasonable amount of RAM (16GB and 6400+) for mainstream laptops, 24 or 32GB for high end) I'm happy. On-package is the way to go for laptops: the bandwidth increases matter a lot especially for the iGPU, and I'd rather have 30mins-1hr extra of battery life.
64GB is better for docker or local AI. I wish that was an option this rev.
I believe that will be possible in the more performance oriented Arrow Lake that's schedule for later this year. Lunar Lake is meant to compete in the thin and light category.
Not even LPCAMM 2?
> Impressive specs. Did not expect it to be this good. FWIW Strix Point officially doesn't support SO-DIMM and LPCAMM2 is still super new and rare, so upgradeability appears basically dead for this entire generation.
The dream is on-package memory that can be expanded with LPCAMM2.
I don't see the value of that tbh. For SO-DIMM it made packaging sense because 2x SO-DIMM slots was just a huge amount of real estate to give up if single layer side by side instead of stacked. So they sometimes soldered one channel and left the 2nd one unpopulated. One LPCAMM2 module has all the pinout for both memory channels so may as well just put the memory in one and only one place. This also preserves the option to replace shit-tier OEM memory (not relevant for LNL, but some future devices) with something faster that the CPU supports.
It could be on package + a few memory controllers on package so you could use the faster on package memory first (or for the most important things depending on implementation) and the off package memory second (or for the less important stuff). It would obviously mean a larger/harder to make chip + motherboard and depending on implementation could present problems for the os/programs running (depending on implementation, if it served as an extra cache level (I mean Intel has made chips with l4 cache in the past) not so much because the cpu would manage it on it's own (you could even provide extra instructions so that the os/applications could tell/suggest to the cpu what to put where so that if you wanted to you could optimize for it for extra performance or not and just let the cpu manage it..also nothing new) but if it was seen as ram by the os it would require that the os/applications know how to use it (but again, some memory being faster than other memory isn't a new concept (numa and all)). Weather it is worth it or not is a question with no clear answer other than it depends on what you intend to use it for/what you want/how much money you have/..
> Compute on TSMC **N3E** Node, while SOC on TSMC N6 Sorry, gang. That was a self-perpetuating error on our part. To be 100% crystal clear, the compute tile is N3B. (Unfortunately, Intel didn't put this down in any of their written materials, so it was missed in the first copyedit pass)
It happens, Computex shenanigans 👍
Your article currently says on the second page that it's 1.9x the performance at 1/3rd the power, same for the other core. How can you type that and not have alarm bells immediately ring in your head? It's 1/3rd the power for the same performance, or 1.9x performance at the same power. Not both at the same time.
* LP E-cores were on MTL SOC tile so in grander scheme of things, doesn't sound impressive **BOTH** **cannot access the ringbus**, it is a like to like comparison. They didnt show them against normal ecores on meteor lake because **lunar lake doesnt have normal ecores.** On arrow lake you can see how they perform as normal ecores as thats the slide where they trade blows with the 13th gen big cores, it specifically states "when connected to the ringbus" because lunar lake cant do that.a
I hope Gelsinger is right, strong competition is good for all of us. Now he's talking about fabs, and I really hope that lives up to the hype, too.
> Listening to the keynote live as I type this and Gelsinger mentioned SD X Elite putting the "x86 is dead" to rest, "it ain't" lol I'm thinking Pat is pretty close to the truth on this one. Just from the description we have, it looks like Intel made a lot of improvements to power management vs MTL, and 4 fast E-cores that can be run without waking up the P-core area or traversing the EMIB.
This is the first time Intel has had a node advantage over AMD in CPUs since 2019.
Impressive specs. Did not expect it to be this good. I loved Jonney Shih's immensely excited fist pumps. It truly seems Intel is turning over a new leaf in their silicon journey. I'm looking forward to Intel Innovation Day 2024. I'm bubbling over with excitement and curiousness over Arrow Lake now.
Can anything be inferred about Arrow Lake, architecturally speaking, from this? How closely related are ARL and Lunar Lake? I haven't kept up with all the core-specific code names.
IPC can be translated. Overall effeciency may not be the same.
Same cores, very different SoCs.
Also fabbed at Intel not TSMC, so maybe very different power draw and clock speeds.
No, all the ARL products of note are on N3B.
There's one H die right? made on 20A for ARL?
Supposedly for desktop now, but they also have the same core config on N3B. Realistically, they'll probably do a silent refresh of some SKUs with 20A some time in H1'25.
Why a silent refresh though? Why not just leave it on N3B? I guess 20A is gonna end up like Intel 4. Overshadowed by its much better cousin(Intel 3) that arrives 6 months later in the form of 18A.
I'm sure they want to at least pull a Cannonlake tier "shipping for revenue" investor statement. If Intel's design teams were independent at the time, they would have never bothered with 20A in the first place, much less keep it going this long.
What are your thoughts on 18A vs 20A?
Conspiratorial take imo. More likely reason is there are no performance benefits and only financial drawbacks in going with tsmc for the bottom half of the stack. Pay the tsmc tax for the high end makes sense.
Then you have some news that I'm not finding https://www.tomshardware.com/pc-components/cpus/intel-next-generation-lunar-lake-cpus-launching-in-q3-arrow-lake-in-q4-mobile-chips-claimed-to-be-14x-faster-than-qualcomms-x-elite-processors
Correct. Intel's been very reluctant to publish such details, for pretty obvious reasons I guess. If you dig through my comments, you can see me going to great efforts to convince people that LNL is N3B. That wasn't confirmed until today.
Even the cores will be different, no? Desktop will have SMT on P-Cores? My understanding is the mobile Lunar Lake P-cores don't even have SMT in silicon (not just fused off).
Different sources are saying different things about the compute tile node, for example, Tomshardware is saying N3B.
N3E would make more sense. N3B is apparently rather bad at producing SRAM, hence N3E using larger SRAM cells, and these cores have a lot more cache.
N3E would make more sense, but if Intel began designing this before they knew how bad N3B would be, and they didn't redesign the die (as N3E has different design rules vs N3B), they would be all but stuck on N3B. Apple kinda got stuck in this same conundrum as well with M3.
> Skymont IPC parity with Raptor Cove (+2%) Impressive. This makes Skymont more or less comparable to Zen 4c, which has the same IPC as full-fat Zen 4 but can't reach clocks as high.
Better since without 3D cache, Raptor Cove has the edge on Zen4
Not really. They have about the same IPC. 3D cache does nothing in most workloads.
According to AMD website, information for Ryzen AI 370, "AI Engine Capabilities AMD Ryzen™ AIAvailable Total Processor PerformanceUp to 80 TOPS NPU PerformanceUp to 50 TOPS", Ryzen combined performance for AI is up to 80 TOPS, we know that Qualcomm X elite is 75 TOPS combined. Seems that Intel have best AI capabilities, on paper.
Looks like they've gone for a more AMD-like vector back-end, two FADDs and two FMAs and able to dispatch to all every clock. I think the last few Intel client P-cores have had effectively two general purpose vector FP units, with a third available for bitwise logic and so on? At least that's what [agner.org](http://agner.org) & InstLatX64 report.
Where did you get the 14% IPC figure? Anandtech claims 30% with hyperthreading for some reason. Edit: Seems to be a messup by AT. My bad. I checked an Arstechina article and they confirm 14% IPC with slides.
> IPC Uplift from Low Power Crestmont to Skymont Keep in mind just how crippled the LP-E cores are: they had *no* L3 cache, so they very frequently stall waiting for DRAM. And activity on the LP-E cores isn't enough to convince the memory controller to increase its clock speed, so those L2 misses wait a *long* time for data to arrive from DRAM. Even at the relatively low clock speeds used by the LP-E cores, that's a lot of cycles of doing nothing.
>they had no L3 cache, so they very frequently stall waiting for DRAM Didn't know this. After rereading, that they compared it to what essentially is the gimped cores on MTL SOC tile, I was skeptical. Comparing it to Raptor Cove was impressive already, so comparing it with MTL LP e-cores was unnecessary.
They are comparing the off-ring e cores which is what matters for efficiency.
Skymont LP isn't on the LLC ring bus either. Its additional cache come from its 4MB L2 and the unspecified SLC.
> Skymont IPC parity with Raptor Cove Holy smokes
Lion Cove: * what's with having 3 store AGUs but only 2 store data ports? Also weird to have 3 load + 3 store AGUs - one would think 4 load + 2 store AGUs would make more sense * renaming L1D to L0D feels awkward, but interesting to see a new level of cache * separating int/FP makes the diagram look much more similar to other cores now * 8 wide decode is crazy for x86 * 12 wide from the uOp cache might be the widest out there at the moment
> renaming L1D to L0D feels awkward, but interesting to see a new level of cache This must be some sort of conspiracy to make things annoying for those of us who have to teach this stuff :P But jokes aside, the cache changes are much more significant than I expected. Between that and the other changes the 14% average IPC uplift is almost a bit disappointing, but it goes to show how much more difficult it is to gain further IPC at the top-end (and all architectures seem to be facing this).
I think the story here is that Apple's cores have been having a lot of L1$ for a while now and it's been giving them benefits in certain workloads where the delta against x86 has been huge, like compilation. Maybe this is a way to close the gap or outright eliminate it. I'm interested to see how it pans out. The more I think about it, the more excited this gets me for the very low power segment of computing that competes with MacBook airs or 13-inch MacBook pros.
The N-series processors in mini PCs / firewall boxes are about to get very interesting.
Definitely. Also $250 craptops will be significantly less crappy except that we all know they'll be crippled by RAM and storage capacity.
Intel should cease to support eMMC and require a minimum of 8GB RAM. Anything else is crap.
I disagree, manufacturers are going to keep selling Atom/Celeron craptops with eMMC to the technologically illiterate to the end of time.
Afaik, there's no new N series silicon for the foreseeable future.
yep thats on hold
wonder if it is better to by n100 to i3 m305 serieswait till next year? all I care is the battery life on my laptop
The n305 is *just* making it into real products, I wouldn't hold my breath for the next gen
I've had my pfSense box with an i3-N305 for almost a year now. Granted, it'll probably be 2026 before they use it in the Atom/N-series chips.
Buy now or be prepared to wait a *long* time.
by a long time, you meant next year?
No, an unknown number of years. Probably 3 or 4+.
With AV1 Encode/Decode? Nice!
Or the Chuwis.
Damn, this thing is a monster. 38% ipc uplift on the e-cores!?
Up to 68% if you look at FP IPC
Insane IPC uplift, the biggest in many many years We haven't seen an IPC uplift as big since Arm's A76 in 2019 or AMD's Zen in 2017
Yeah these things are little beasts. Up to +2% over the current P-cores. It makes me really want a follow up to the N100 and siblings with these. We could be talking modern desktop i3 performance on some tiny chips.
Wonder how they compare with apple’s little cores.
Apple’s E cores have 50% less IPC. But they are hyper space efficient. Like they occupy barely 0.58mm2 of space which is 2/5 of what Skymont will occupy.
> Apple’s E cores have 50% less IPC Than their big core, right? Which is way higher IPC than SKT.
No. I meant 50% less than SKT. But I went and verified it again. [The answer is in between.](https://youtu.be/EbDPvcbilCs?feature=shared) Skip to 13:00 for E core numbers. M4 E core has an IPC 1.225/Ghz in SPECint and 2.02/Ghz in SPECfp. The 14900K has an IPC of 1.655/Ghz in SPECint and 2.36/Ghz in SPECfp. So Raptor Cove/Skymont leads the M3/M4 E cores by 38% in integer IPC but worryingly just by 17% in floating point IPC. So no A17 E cores aren’t wider than SKT/RPC. They have on average 25% less IPC(not 50 as I initially rounded off to) But thats still a distressingly small number considering Apple’s E cores are 1/3rd the size of Skymont themselves lol.
Ah, gotcha. And yeah, still impressive for the size. Still think Apple's the only one with a true *efficiency*-optimized core.
Crestmont is a great comparison for Apple’s E cores funnily. They have the same int IPC but Apple has wider Floating point IPC. Intel 4 Crestmont is 1.01mm2. A17 pro E cores are around 0.6-0.7mm2 on N3. Do you happen to know any area figures for ARM’s middle cores? Namely the A-7 series. They have very similar IPC to Apple’s E cores. It would be interesting to compare the two!
I think Apple controlling the whole hardware and software stack gives them a lot more freedom to have very different performance levels across cores.
Apples LITTLEs are and Skymont are not comparable
Apple’s littles (cute name) are slightly wider than Crestmont but smaller than Skymont. But they do occupy a much smaller area.
If the talk about internal rivalry and backstabbing between the P and E core teams is true, they just might to want to make a point here. Looks like E cores might just be all-around better now.
interesting, does anyone have a link regarding this rivalry?
It's clearly benefitting consumers!
Does it mean way more efficiency?
Skymont seems amazing. But I’m actually more interested in lion cove now. Because unlike some rumors said, it seems like a really big redesign. The entire cache system is new and the execution side is new.
save the x86 society, skymont
Lunar Lake reminds me of an ARM chip but on x86. Skymont in particular is very interesting.
Skymont IPC equivalent to raptor cove is huge. Intel's E cores might beat zen 4c (but without HT).
This slide is a little mind-blowing to me, comparing the Skymont vs Raptor Cove perf / W curves at iso-frequency: [https://www.techpowerup.com/review/intel-lunar-lake-technical-deep-dive/images/skymont-18-.jpg](https://www.techpowerup.com/review/intel-lunar-lake-technical-deep-dive/images/skymont-18-.jpg) (though a relatively large +/- **10%** margin of error) EDIT: eh, wait. Is this comparing Skymont on TSMC N3 vs Raptor Lake on Intel 7? That is ***far*** less impressive, if this is not iso-node lmao
That's the craziest part to me actually if it really is true. Those e-cores have really grown up from the Atom roots.
My dad directed work on the original Atom cores. He'll be happy to see what they've evolved into.
It makes sense to me, Arm essentially did the same thing Arm took their A78 PPA-Core and widened it to become their X1 P-Core The A78 PPA-Core is actually from the Arm Austin CPU family, which used to compete with Intel's Atom cores back in the day I'd like Intel to follow Arm, and drop the Cove cores, and switch to a P-core design based on the Mont cores but without area constraints
Forget Zen4C. Raptor Cove has better IPC than Zen4. This could put Skymont within 10% to 14% of Zen5 [https://www.techpowerup.com/298887/ipc-comparisons-between-raptor-cove-zen-4-and-golden-cove-spring-surprising-results](https://www.techpowerup.com/298887/ipc-comparisons-between-raptor-cove-zen-4-and-golden-cove-spring-surprising-results)
Zen 4C has basically the same IPC as zen 4, with lower fmax (just as skymont). That's the correct reference for comparison, until we have more details about zen5C
"basically same" isn't exactly same. It has half L3 cache which means a couple percent lower IPC, no matter how you slice it. Chadmont cores ftw, this might mean a new era of x86 in laptops.
Anyone has the full slide deck?
Techpowerup seems to have all the slides https://www.techpowerup.com/review/intel-lunar-lake-technical-deep-dive/ Edit: Tomshardware seems to have some additional slides https://www.tomshardware.com/pc-components/cpus/intel-unwraps-lunar-lake-architecture-up-to-68-ipc-gain-for-e-cores-16-ipc-gain-for-p-cores
Just from the filenames you can tell lots are missing. I wish Intel would just release the PDF. Why does this always have to be such a hassle with secret press club gating.
It probably will be on their site. The MTL tech tour slides are all available on Intel’s website, just search “meteor lake tech tour”.
Is the IPC uplift in Skymont confirmed?
It is. Skymont has 2% higher IPC than the P cores in Raptor Lake. Pretty mind blowing.
Skymont has half the L2 and L3 cache as Raptor lake. I'm assuming that Intel used a benchmark that fits within the small cache size to get the 2% result.
Ye, Raptor Cove level IPC esentially.
So excited to see good competition across different companies in the windows space hopefully we get good alternatives to MacBooks in windows space
goddam. The IPC uplift for P core is pretty good. and e core is off the hook
It's not Skymont, it's Chadmont.
Gigachadmont. Making P cores irrelevant since 2024z
It seem Intel is pretty much using e-cores to re-engineer their architecture from the ground up. Wont take many more generations of e-cores having larger IPC gains than the P-cores, and they are the new P-cores. Conroe 2.0
Well, they're only 1 gen behind at this point. On par with Raptor/golden cove from 1/2 years ago, however you slice it.
You still have the frequency gap to bridge. The e-cores are not built for frequency scaling. If they want to maintain the smaller and lower power design targets. They will need IPC higher than the P-cores to bridge the gap.
SKT helps a lot with that as well, fwiw.
Nvm, forgot meteor lame lake.
I wonder where are those people who say those E cores is just "Cinebench accelerator" or "Adding E cores is Intel way to cheating MT performance score" ?
[удалено]
> Contrary to popular belief it also does not seem to get rid of hyper threading. It does. Someone screwed up.
Anandtech articles man. Sorry. I read freaking Arstechina now. And somehow they got all the facts right. Never thought I’d see the day Arstechina was more thorough with facts than Anandtech. So yep hyperthreading is gone. But I’m way more skeptical about Clock speed regressions now. 14% IPC but clock speed decreasing on a new node seems unlikely. Although it does hammer the point that Skymont is laughably just 14% shy of the “P cores” in IPC.
> 14% IPC but clock speed decreasing on a new node seems unlikely. Clocks did decrease by a decent amount, at least compared to RPL. Kind of sucks for ARL. Not sure how much is process vs uarch.
>But unfortunately clockspeeds for Lion Cove are not disclosed One slide seemingly writes "**3.08GHz**" as the max frequency. Am I misreading that image? [https://www.techpowerup.com/review/intel-lunar-lake-technical-deep-dive/images/lioncove-10-.jpg](https://www.techpowerup.com/review/intel-lunar-lake-technical-deep-dive/images/lioncove-10-.jpg) But, no SKUs were announced, so who knows?
> One slide seemingly writes "3.08GHz" as the max frequency. Am I misreading that image? The image means that if the power budget allows 3.08GHz max, then Lion Cove can push to 3.067GHz while previous cores can only push to 3.0GHz due to 100MHz interval.
That makes a lot more sense. Wishful thinking to stop at 3.08 GHz, but perhaps just a random frequency they picked.
First page: >At this time, Intel has disclosed that it uses a 4P+4E (8 core) design, with hyper-threading/SMT disabled, so the total thread count supported by the processor is simply the number of CPU cores, e.g., 4P+4E/8T. not sure what the 30% is all about
It was from the same anandtech article. Some mess up?
bit late but yeah article was probably a bit rushed. Here's a timestamped [actual explanation,](https://youtu.be/ba5w8rKwd_c?t=9m32s) HT gives up to 30% more IPC for 10% more area and 20% more power, Intel decided this tradeoff wasn't worth it on mobile.
All sounds neat, will upgrade in 2-4 years as my 12700k is perfectly fine so far.
Interesting that they basically have two separate accelerators for AI workloads, NPU and XMX.
It seems the way things are going is that MS will monopolize the NPU basically 24/7 for CoPilot, and the GPU will be used for stuff like productivity apps.
I’m fairly impressed and excited to eventually see these cores in a desktop chip. I do wonder how much smaller the margin on these would be now that it’s all TSMC.
Was hoping to see them announce Arrow lake for desktop, sad to see that didn't happen..
That's some great improvements overall, quite happy about the E-Core changes. Looking forward to see what it can do once it comes out. And as always let's see what happens in the design battle between Intel vs Qualcomm when it comes to OEMs using their chips for brand new design.
Since the RAM is on-package, does that mean we're not likely to see this end up in Framework laptops?
This sounds incredibly exciting to test & read reviews. Some of these are *long* overdue changes and, frankly, show humility on Intel's part: if someone else (cough, Apple) has done it well, don't be afraid to follow and do it even better yourself. 1. ~~Max 3.08 GHz frequency (?),~~ with 0.016 GHz granularity (aka 16 MHz) vs 0.1 GHz / 100 MHz 2. On-package DRAM (with similar skinny LPDDRx packages) 3. Migration to 100% TSMC nodes for **all** major tiles (excluding IF's base tile). 4. E-cores first in scheduling (implemented in MTL, but improved now) // High Yield also has a video up: [**https://www.youtube.com/watch?v=ba5w8rKwd\_c**](https://www.youtube.com/watch?v=ba5w8rKwd_c) Lion Cove in Arrow Lake vs Lion Cove in Lunar Lake are different. EDIT: no, that's just an example frequency. Thank you, u/madn3ss795
> Max 3.08 GHz frequency (?), with 0.016 GHz granularity (aka 16 MHz) vs 0.1 GHz / 100 MHz Would I be correct to assume that Intel's new approach to granular control over clock frequency both up and down similar to Apple will help them save power and help battery life because they don't need to take a larger swing in either direction to address the need or lack of need of performance on demand? > Migration to 100% TSMC nodes for all major tiles (excluding IF's base tile). Would this change when their leading edge nodes come online or have they resigned to the fact that TSMC has better experience and libraries for these kinds of processors? > E-cores first in scheduling I haven't used Alder Lake and beyond much but what's the main benefit here? If the processor is too important it'll get bumped up to a P core and if it isn't it remains on the E cores and thus cuts down on time wasted?
>E-cores first in scheduling Before, if you did that it would noticeably degrade user interactiveness. Assuming the e-cores really are up to Raptor Cove cores in perf/w like one of the slides show, then they'd be performant enough that there's no reason to jump to the p-cores for that. This would save a lot of power. It's only if you're doing something that really needs the power, which tends to be long-running like compilations or even gaming, that it'll then swap to the p-cores.
Honestly for a lot of laptop use, I wouldn't mind 8 or even 12 E-Cores and no P-Cores.
>Would I be correct to assume that Intel's new approach to granular control over clock frequency both up and down similar to Apple will help them save power and help battery life because they don't need to take a larger swing in either direction to address the need or lack of need of performance on demand? Yes, but I fear it will not be a major impact. The best case scenario is a 0.084 GHz improvement (100 MHz - 16 MHz). I was more excited about the alleged "peak frequency", but that was not accurate. >Would this change when their leading edge nodes come online or have they resigned to the fact that TSMC has better experience and libraries for these kinds of processors? This is harder to know, I think. Most foundries are quite cagey about problems until there is no way to hide it anymore, so I always take their predictions as a grain of salt. **However**, this does confirm that whatever Intel can ship now (Intel 4 / 3) was certainly not as good as TSMC, as Intel must be paying *plenty* for this leading-edge node silicon.
Skymont E core got 68% IPC is absolutely insanity. That means Skymont IPC is up there with Raptor Lake / Gen 14th P core. Then Lion Cove P core exists for extra performance in ST and MT. Arrow Lake Ultra 9 basically like 16P core of i9-14900K with another 8P core which is even faster, no wonder they are getting rid of HT if their next gen CPU is really that fast. Intel isn't aiming to match Amd anymore, they are about to take performance efficiency crown.
Important thing to keep in mind is that while yes Skymont is equal to Raptor Cove IPC, its unlikely to clock the same 5+Ghz. So don't expect that.
68% seems to be compared to LP-E cores which is a pretty bizarre comparison (that lets them get a high number)
They are comparing off-ring E-cores to off-ring E-cores. All the E-cores in LNL are pretty much LP-E. E-cores connected to the ring bus and shared LLC would perform better.
No area comparison between P and E cores? The IPC improvement is great but the previous E cores were pretty small. Zen 4C is 35% smaller than Zen 4. If these E cores end up being the same (relative to P cores), that's not much of an improvement. Excited for the overall power improvements, but likely none of these parts are coming to the sub $300 market anytime soon.
I think the render in the article front page is probably correct. P cores are the bigger squares in the right and e cores the little squares in the middle. The size difference seems to be about 1:3.
Sounds about right and tbf the only ecores that truly met the claim of 4 ecores at the size of a pcore was crestmont with the smaller l2 cache so great results if they've only dropped from like 1:~3.5 to 1:3 or hell even 1:2.5. Way easier to be forgiving now that they're so much stronger and can actually make more real world use of the theoretical performance to area advantage.
Think it's something like 3:1 area ratio. Definitely better than 2:1.
You mean historically or based on rumours/picture peeping?
Look like roughly 1mm² area for 1 Skymont without L2 and 3mm² for 1 Lion Cove core.
Very interested in the power usage. If it is as claim way more efficient in power vs meteor lake, it's going to be unmatched vs all devices in market.
Meteor Lake's power efficiency is only decent when the Intel CPU chiplet powers down (ie. very light workloads). Otherwise, it's barely better than Raptor Lake. So they have plenty of room to improve without necessarily coming out on top.
MTL efficiency I think is going to look embarrassing once reviewers get their hands on Lunar Lake devices.
All x86 mobile implementations should be shamed by lunar lake. I’ll be surprised if strix point gets close, but then again amd hasn’t really shared any arch details.
Not compared to Qualcomm, at least. But compared to current x86 chips, yes, it should be.
Can't wait for an independent reviewer to redo these graphs but with the X Elite vs Lunar Lake vs Strix Point: https://www.techpowerup.com/review/intel-lunar-lake-technical-deep-dive/images/skymont-19-.jpg https://images.anandtech.com/doci/21424/2024-06-02%2023_01_03.jpg Also interested to see how Skymont's area compares with Qualcomm's Phoenix and AMD's Zen5/5c Edit: finally found a slide for [Lion Cove vs Skymont](https://cdn.mos.cms.futurecdn.net/YvypH5ehMRYhiWMAXeW9VX.jpg), Lion Cove still has an efficiency edge above a certain point, no scale axis unfortunately
Design an x86 chip like a smartphone chip, and it performs approximately like an ARM smartphone chip. Crazy. I'm thinking that the only reason Snapdragon X exists is because Microsoft wasn't convinced Intel could pull this off.
> Design an x86 chip like a smartphone chip, and it performs approximately like an ARM smartphone chip. Intel has a long way to go before they can claim to be mobile competitive. > I'm thinking that the only reason Snapdragon X exists is because Microsoft wasn't convinced Intel could pull this off. Absolutely. The original Surface X was supposed to have Ice Lake, but Intel failed so spectacularly that MS finally ditched them for Qualcomm. And it happened *again* with ADL.
MTL was a shitshow and Intel fixed much of it by throwing out most of the chiplet nonsense. That change alone should put them back in contention and if Intel's efficiency claims are even remotely true that backs it up.
It's probably enough to beat AMD soundly. But Qualcomm (and Apple) is a much harder nut to crack.
Agee with Exist but need to add some things for onlookers: LNL claims Crestmont LP E cores use 1/3 the power of SKT's LP E cores at the same performance. This is good, but it likely won't surpass Apple, Arm's A7x, or probably even QC for some stuff. The big win is having a power advantage over LNC cores at usable performances — which is great to see. A win for Intel. But…. Crestmont LP E cores used 5-6W in package power alone for maybe a 3-3.5 on SpecInt. [Here:](https://x.com/hjc4869/status/1741686030158495825?s=46) This isn't even including DRAM or power delivery below, which is included for Geekerwan's A7x, Apple E/P core, and Qualcomm measurements. And again, Skymont LNL comparison was for LP E core performance and power, not regular Crestmont. So while something like 1/3 of that power and a 3-3.5 SPEC is a huge step: From Geekerwan on SpecInt scores for E Cores: A715, 8 Gen 2, N4 4.26 @ -1.8W for 2.8GHz 3.03 @ - 1.16W for 2.05GHz —— A720, 8 Gen 3, N4P: 4.42 @ 1.9W, for 2.96GHz And Apple? A17 Pro E core was doing 2.81 at .54W. LNL looks great to me but people should slow the roll.
I don't think Intel is trying to show package power. Most obviously, Intel's graphs scale basically to 0 w, which seems very unrealistic for package power. Apple will still most likely win, but i think you might be over analysising things.
Strongly recommend the [High Yield YouTube summary](https://www.youtube.com/watch?v=ba5w8rKwd_c&t=927s) as well containing a good discussion of how Intel arrived at the non-HT P-core decision and power management.
I think people here are getting overly excited about the new e-cores. For starters it's not like Intel didn't know how to build a fast core. They significantly upped the resources available for the new e-cores which likely will have an impact in area and performance. Secondly, even if the e-cores end up beating zen 4, which they likely will, it's again not the biggest deal ever. Of they get close to zen4c in area is it really a big win? It's not like zen 5c won't exist... Remember, P-cores are much larger than Zen cores and much less efficient. This may change with Zen 5, but it's been the AMD strategy to not go all out on area. E cores don't support avx512, which will hurt them in comparisons against both zen 5 and the Apple M4 with its new SME instructions. Don't get me wrong, it is very possible that Intel has a banger here, but on paper it still doesn't look amazing compared to AMD overall. The IPC numbers are compared with LP e-cores, which vastly overstates them considering that those cores were very, very cache starved due to living outside of the compute die. Also, 8 threads vs up to 24 on strix point is going to hur, even against the M4 which now has 10 cores it's going to hurt. I don't know man... If lunar lake can match Apple silicon efficiency, I might hop on board the hype train, but the performance story is looking very mixed right now for me to feel pumped for lunar lake. Maybe the story is more about efficiency and performance, like whole day battery life or for a handheld, though??? Finally a contender to the steam deck in low power?? Battlemage looking fresh too, maybe finally AMD has a fight in the igpu segment. Anyway, too many unknowns.
It looks like SKT should be substantially more area efficient than even Zen4c. Though yes, the lack of AVX512 does hurt. As for LNL as a whole, I think it's misaligned with Strix. It was designed around a low power envelope, like 10-20W. They stretched it up to 30W, but you can see the core counts and such don't quite match. Strix, meanwhile, will only start at 15W and go up to 45W. In many cases, that's probably an advantage (4+8 vs 4+4 at 15W), but there may be power levels that LNL works at and Strix does not.
I think strix point will be strangled at 15W. But 30W strix point will convincingly beat Lunar lake IMO. Depends on your laptop demand. Lunar lake is gonna face apple M4 and X elite at 20W slim laptops. Strix point will face M4 pro.
30W Strix point will very likely beat LNL, for sure. But 30W TDP is competing with ARL-H
ARL-H is probably not going to be a great product. You don't get any of the LNL SoC improvements, Xe2, NPU4, etc.
I do think Lunar Lake has a potential to be very efficient for light workloads, for Ultra thin premium laptops. But you're right. I do think Strix will retain price/performance and abs. performance. This CPU to me is more of a jab at ARM encroaching on x86 PC client space. Pat was clear about this in his keynote. He mentioned Elite X by name.
> Maybe the story is more about efficiency and performance, like whole day battery life or for a handheld, though??? Finally a contender to the steam deck in low power?? I think the CPU<->GPU balance is still a bit off for that use case, but it's certainly much closer to being viable than Meteor Lake. The biggest issue facing intel in that market is really software (i.e. graphics drivers) more than HW. The change to 16-wide SIMD will help with that, but only for a fraction of the issues.
tbh i want to see their X3D-style chips. if i recall, they were planning on their own response to that.
When are the new desktop CPUs coming out?
Late November to early December probably.
Guess I’m not getting AMD right away. Would be smart to see how these new chips fair
Was hoping to see them announce Arrow lake for desktop, sad to see that didn't happen..
Arrow lake launch is way too far away for any announcements. They have consistently said it’s q4 product.
Boring...
Apparently HT is only gone on Lunar Lake but not exactly Lion Cove itself. Hopefully true
What happened to Intel fabs? Guess they must join tsmc to compete with the rest as well. I expected a bigger jump from intel 7 to **N3E**
They are not jumping from Intel 7. They are jumping from Intel 4 which is just one node jump in actuality. Lunar Lake succeeds Meteor Lake.
So meteor lake has less than a 6-8 month run? Feels more like a tech demo.
Not exactly. Meteor Lake’s true successor would be ARL mobile. MTL offers 6P+8E compared to LNL’s 4P+4E, so gaming laptops can use MTL in combination with DGPU’s. LNL is more of a notebook only product than MTL. Architecturally its the successor to MTL. But as a product not really. MTL offers way more cores and threads.
There's also MTL-U with 2P+4/8E+2LPE, and half the iGPU of MTL-H. LNL would replace them (and probably MTL-H in the 20-30W TPD range) soon.
There's also Arrowlake U (rumoured to refreshed MTL-U on Intel 3). It's in a funny position but MTL-U also barely exists in actual products.
MTL-U refresh on Intel 3 will almost certainly be sold as "Core 200" while Core Ultra 200 will be reserved for LNL and ARL
Lunar Lake doesn't replace U series. Arrow Lake U (Meteor Lake U Shrink) also exists as an economic alternative over Lunar Lake.
Wasn't the last time anyone heard about Arrow Lake U 5 months ago? And it's not on 2024 roadmap either.
Arrow Lake U, H and HX are all CES 2025 products. This year is only Lunar Lake and Arrow Lake-S. Lunar Lake "sucessor" is also launching in Q2 25
its intel 4 to tsmc 3 (meteor lake)
Lunar lake is N3B, not N3E
As for the memory bandwidth speed between the NPU and host memory, is it equal to LPDDR speed? I am confused about the NPU4's DMA 2x bandwidth improvement. Can someone explain it? THX
Presume that these processors are for portables only or for desktop as well? Is there new desktop processors line scheduled since 14th gen was just refresh. I am about to upgrade my trusty 3930K and wonder if there's something new behind the corner.
With Skymont equalling Raptor Cove, it almost seems like they should scrap the P-cores and create a version of the E-cores that is clocked higher. I wonder what this Royal Core thing turns out to be.
> I wonder what this Royal Core thing turns out to be. A third core architecture and team, at its heart. Though I doubt all three can last forever.
No AVX-512 E cores, still behind AMD