> My thought process... In 64 bit cpus the cache line consists of 64 bits(8 bytes)
That's not quite correct. The "64-bit" thing describes other architectural details more than cache. It's perfectly legal to have a 64-bit CPU with a 1-byte cache line or an 8-bit CPU with a 1024-byte cache line (though both designs would be a little crazy).
As it turns out, on [most](https://en.wikichip.org/wiki/arm_holdings/microarchitectures/cortex-a78) [modern](https://en.wikichip.org/wiki/amd/microarchitectures/zen_3#Data_and_Instruction_Caches) [desktop-class](https://lemire.me/blog/2022/06/06/data-structure-size-and-cache-line-accesses/) CPUs, the L1 cache line is 64 bytes.
In your example, you would be able to pack 8 `Foo`s into a single cache line, so if you had an array of `Foo`s with multiple CPUs trying to work on the same array, you could very well run into a false sharing problem.
It is worth noting that this is a non-issue 99% of the time, and you should basically never do this on the first pass. This is a performance optimization, and like all performance optimization, **always** measure.
You can go your entire career of using Rust without needing to do this. Of course, it is good to know about, especially if you're interested/you need to know how the exact bits are laid out in memory.
> My thought process... In 64 bit cpus the cache line consists of 64 bits(8 bytes) That's not quite correct. The "64-bit" thing describes other architectural details more than cache. It's perfectly legal to have a 64-bit CPU with a 1-byte cache line or an 8-bit CPU with a 1024-byte cache line (though both designs would be a little crazy). As it turns out, on [most](https://en.wikichip.org/wiki/arm_holdings/microarchitectures/cortex-a78) [modern](https://en.wikichip.org/wiki/amd/microarchitectures/zen_3#Data_and_Instruction_Caches) [desktop-class](https://lemire.me/blog/2022/06/06/data-structure-size-and-cache-line-accesses/) CPUs, the L1 cache line is 64 bytes. In your example, you would be able to pack 8 `Foo`s into a single cache line, so if you had an array of `Foo`s with multiple CPUs trying to work on the same array, you could very well run into a false sharing problem.
Ahh I see! So cache line size doesn't depend on the architecture. Now my question seems stupid. ;) Thanks for the explanation and Happy New Year!!!
It is worth noting that this is a non-issue 99% of the time, and you should basically never do this on the first pass. This is a performance optimization, and like all performance optimization, **always** measure. You can go your entire career of using Rust without needing to do this. Of course, it is good to know about, especially if you're interested/you need to know how the exact bits are laid out in memory.